Latest Custom Compiler Custom Design Tool Now Available With Visually Assisted Automation

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Summary of the press release:

Synopsys offers the Custom Compiler ™ version 2018.09 custom design tool with performance enhancements and improvements that reduce closure design time for custom integrated circuit design. The tool is now added with Extraction Fusion and DRC Fusion with IC validator. The compiler’s visual assistive automation technology automates custom layout tasks, and the template wizard provides the ability to reuse or adapt proven layouts on silicon.


Original press release:

Synopsys Custom Compiler Doubles New Customer Adoptions and Introduces New Version

New fusion technologies reduce analog design shutdown time

MOUNTAIN VIEW, Calif., Oct.23, 2018 / PRNewswire / –

Strong points:

  • New Extraction Fusion and DRC Fusion technologies enable tighter design / layout collaboration and fewer late-stage design iterations
  • Visual Assisted Automation Proven to Deliver 2-10 Times the Productivity
  • User community expands to over 3000 designers with significant increase in new customer adoption

Synopsys, Inc. (Nasdaq: SNPS) today announced that new customer adoption of its Custom Compiler ™ custom design tool has doubled over the past year, thanks to the proven benefits of its innovative technologies. automation of the visually-assisted layout. Custom Compiler users have improved the productivity of custom design by 2-10 times over previous solutions, especially for advanced process nodes. Synopsys also announced the release of the latest version of Custom Compiler, version 2018.09. The 2018.09 version of the custom compiler includes performance improvements and improvements that reduce the design time of the closure for the design of custom integrated circuits (ICs). Important new features in this release include Extraction Fusion (with StarRC ™ technology) and DRC Fusion (with IC Validator technology). These provide custom IC designers with early approval quality spurious feedback during the design process and approval quality design rules (DRC) checking during layout.

New extraction and smelting technologies in the DRC

Extraction Fusion and DRC Fusion technologies reduce the time required to complete the analog design closure. Extraction Fusion allows you to extract layout glitches from a partially completed layout. This provides circuit designers and network designers with earlier feedback of network noise. Circuit designers can use early glitches to refine their designs and avoid reworking the layout. Layout designers can use early glitches to confirm that they meet design specifications. DRC Fusion enables live verification of design rules during layout using IC Validator. By checking for layout errors, designers can reduce the number of end-of-cycle iterations caused by design rule violations discovered during final approval review.

Proven visual aided automation to reduce layout time

Custom Compiler’s visual assistive automation technology automates custom layout tasks by leveraging the graphical usage model familiar to layout designers, rather than requiring complicated constraint entry and scripting like in competing solutions. Custom Compiler users have shared their results of deploying visual-assisted automation in presentations at Synopsys User Group (SNUG®) meetings around the world, and the results have been impressive. In some cases, design time has been reduced by up to 90%. The latest enhancements further improve the user experience and reduce design time, according to feedback from early adopters.

“Custom Compiler’s enhanced model wizard improves our ability to reuse or adapt layouts already proven on silicon, giving us better quality layouts, faster,” said Atul Bhargava, senior CAD manager at STMicroelectronics. “Along with the gains from other Custom Compiler features, we are seeing a significant reduction in the analog layout development cycle. Gain is maximized for analog layouts but is useful for all layouts, in general. “

Growing adoption of custom compiler clients

The adoption of the custom compiler has grown rapidly and has now exceeded 3000 users worldwide. The adoption was driven by customers who value a modern, open platform built for productivity, especially at the advanced node level.

“proteanTecs invented new technology that accompanies chip products throughout their lifecycle, from design to production and throughout service. We chose Custom Compiler to help us achieve our goal of achieving better performance. PPA, shorter TTM and increased product quality and quality reliability, while reducing costs, “said Yair Talker, R&D vice president of proteanTecs.” We have deployed a custom-based complete circuit design environment Compiled for our 7 nanometer IP and got tape output in just three months. For our post-silicon SaaS platform that serves the data center and automotive markets. “

“Our development goal for this latest release was to improve customer performance and productivity throughout the workflow, especially for design / layout collaboration,” said Aveek Sarkar, vice president of the Custom Compiler group. at Synopsys. “We have worked closely with leading customers and our own in-house IP development team to identify and resolve key issues encountered in the custom integrated circuit design workflow. “

About the Synopsys Custom Design Platform

The Synopsys Custom Design Platform is a unified suite of design and verification tools that accelerates the development of robust custom designs and AMS. Anchored in the Custom Compiler custom design environment, the platform offers cutting-edge circuit simulation performance, a fast and easy-to-use custom layout editor, complemented by the best technologies for parasitic extraction, analysis reliability and physical verification.

Key features of the Custom Design Platform include Reliability Checking, Visually Assisted Layout, and new Extraction Fusion and DRC Fusion technologies. Reliability-conscious verification ensures a robust AMS design with accurate transistor-level EM / IR analysis, large-scale Monte Carlo simulation, aging analysis, and other verification checks. Visual-assisted automation is a pioneering approach to reducing layout effort, especially for advanced node designs, which has been shown to deliver 2-10 times the productivity. Extraction Fusion and DRC Fusion technologies shorten closure design time and reduce late iterations.

The Synopsys custom design platform is based on the OpenAccess database, includes open APIs for integrating third-party tools, and supports programming in TCL and Python. Platform tools include HSPICE® and FineSim® SPICE circuit simulators, CustomSim ™ FastSPICE, custom compiler layout and schematic editor, StarRC parasitic extraction and IC validator physical verification. For more information, visit www.customcompiler.info.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software ™ partner for innovative companies developing the electronics and software applications we rely on every day. As the 15th largest software company in the world, Synopsys has long been a global leader in electronic design automation (EDA) and semiconductor intellectual property and is also increasing its leadership in security solutions and software quality. Whether you are a system-on-a-chip (SoC) designer creating advanced semiconductors or a software developer writing applications that require the highest security and quality, Synopsys has the solutions to deliver innovative, high-quality, and high-quality products. secure. Learn more at www.synopsys.com.

Editorial contact:
James watts
Synopsys, Inc.
650-584-1625
[email protected]

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